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Carlos's Tech Blog
  • 🧔ECUs
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      • [ZYNQ] Provisioning Guideline
      • [ZYNQ] Decrypting Partition by the Decrypt Agent Using PUF key
      • [ZYNQ] enabling the cryptsetup on ramdisk
      • [ZYNQ] Encrypt external files based on file system using PUF key
      • [ZYNQ] Loading an Encrypted Linux kernel at U-Boot with a KUP Key
      • [ZYNQ] cross-compile the cryptsetup on Xilinx ZYNQ aarch64 platform
      • [ZYNQ] Linux Linaro系统镜像制作SD卡启动
    • S32G_Documents
      • [S32G] Going through the s32g hard/soft platform
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        • S32g2 HSE key config
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        • S32g secure boot signature generation
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        • [S32G] OTA with Secure Boot
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      • [RT-117x] Going through the MX-RT1170 hard/soft platform
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        • [RT-117x]Signing image with the HSM (SignServer)
    • LS104x_Documents
      • [LS104x] bsp project
      • [LS104x] boot flow
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      • [LS104x] Application Note, Using the PKCS#11 in TCU platform
      • [LS104x] 使用ostree更新rootfs
      • [LS104x] ostree的移植
      • [LS104x] Starting with Yocto
      • [LS104x] 使用FIT的kernel格式和initramfs
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      • [IMX6] Defining A U-Boot Command
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  • 😾TECH
    • Rust Arm OS
      • ARMv7m_Using_The_RUST_Cross_Compiler
    • ARM
      • ARM-v7-M
        • 01_ARMv7-M_处理器架构技术综述
        • 02_ARMv7-M_编程模型与模式
        • 03_ARMv7-M_存储系统结构
        • 04_ARMv7-M_异常处理及中断处理
      • ARM-v8-A
        • 02_ARMv8_基本概念
        • 03_ARMv8_指令集介绍_加载指令集和存储指令集
        • 04_ARMv8_指令集_运算指令集
        • 05_ARMv8_指令集_跳转_比较与返回指令
        • 06_ARMv8_指令集_一些重要的指令
        • 0X_ARMv8_指令集_基于汇编的UART驱动
        • 07_ARMv8_汇编器Using as
        • 08_ARMv8_链接器和链接脚本
        • 09_ARMv8_内嵌汇编(内联汇编)Inline assembly
        • 10_ARMv8_异常处理(一) - 入口与返回、栈选择、异常向量表
        • 11_ARMv8_异常处理(二)- Legacy 中断处理
        • 12_ARMv8_异常处理(三)- GICv1/v2中断处理
        • 13_ARMv8_内存管理(一)-内存管理要素
        • 14_ARMv8_内存管理(二)-ARM的MMU设计
        • 15_ARMv8_内存管理(三)-MMU恒等映射及Linux实现
        • 16_ARMv8_高速缓存(一)cache要素
        • 17_ARMv8_高速缓存(二)ARM cache设计
        • 18_ARMv8_高速缓存(三)多核与一致性要素
        • 19_ARMv8_TLB管理(Translation Lookaside buffer)
        • 20_ARMv8_barrier(一)流水线和一致性模型
        • 21_ARMv8_barrier(二)内存屏障案例
      • ARM Boot Flow
        • 01_Embedded_ARMv7/v8 non-secure Boot Flow
        • 02_Embedded_ARMv8 ATF Secure Boot Flow (BL1/BL2/BL31)
        • 03_Embedded_ARMv8 BL33 Uboot Booting Flow
      • ARM Compiler
        • Compiler optimization and the volatile keyword
      • ARM Development
        • 在MACBOOK上搭建ARMv8架构的ARM开发环境
        • Starting with JLink debugger or QEMU
    • Linux
      • Kernel
        • 0x01_LinuxKernel_内核的启动(一)之启动前准备
        • 0x02_LinuxKernel_内核的启动(二)SMP多核处理器启动过程分析
        • 0x21_LinuxKernel_内核活动(一)之系统调用
        • 0x22_LinuxKernel_内核活动(二)中断体系结构(中断上文)
        • 0x23_LinuxKernel_内核活动(三)中断体系结构(中断下文)
        • 0x24_LinuxKernel_进程(一)进程的管理(生命周期、进程表示)
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        • Linux内核调用I2C驱动_驱动嵌套驱动方法MPU6050
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      • 01_OPTEE-OS_基础之(一)功能综述、简要介绍
      • 02_OPTEE-OS_基础之(二)TrustZone和ATF功能综述、简要介绍
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      • 05_OPTEE-OS_系统集成之(三)ATF启动过程
      • 06_OPTEE-OS_系统集成之(四)OPTEE镜像启动过程
      • 07_OPTEE-OS_系统集成之(五)REE侧上层软件
      • 08_OPTEE-OS_系统集成之(六)TEE的驱动
      • 09_OPTEE-OS_内核之(一)ARM核安全态和非安全态的切换
      • 10_OPTEE-OS_内核之(二)对安全监控模式的调用的处理
      • 11_OPTEE-OS_内核之(三)中断与异常的处理
      • 12_OPTEE-OS_内核之(四)对TA请求的处理
      • 13_OPTEE-OS_内核之(五)内存和cache管理
      • 14_OPTEE-OS_内核之(六)线程管理与并发
      • 15_OPTEE-OS_内核之(七)系统调用及IPC机制
      • 16_OPTEE-OS_应用之(一)TA镜像的签名和加载
      • 17_OPTEE-OS_应用之(二)密码学算法和安全存储
      • 18_OPTEE-OS_应用之(三)可信应用的开发
      • 19_OPTEE-OS_应用之(四)安全驱动开发
      • 20_OPTEE-OS_应用之(五)终端密钥在线下发系统
    • Binary
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      • 05_ELF文件_动态链接
      • 06_Linux的动态共享库
      • 07_ELF文件_堆和栈调用惯例以ARMv8为例
      • 08_ELF文件_运行库(入口、库、多线程)
      • 09_ELF文件_基于ARMv7的Linux系统调用原理
      • 10_ELF文件_ARM的镜像文件(.bin/.hex/.s19)
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      • 02_SYS_RUST_文件IO
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        • Openssl EVP to implement RSA and SM2 en/dec sign/verify
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    • Secure Boot
      • JY Secure Boot Desgin
    • FOTA
      • [FOTA] Module of ECUs' FOTA unit design
        • [FOTA] Tech key point: OSTree Deployment
        • [FOTA] Tech key point: repositories role for onboard
        • [FOTA] Tech key point: metadata management
        • [FOTA] Tech key point: ECU verifying and Decrpting
        • [FOTA] Tech key point: time server
      • [FOTA] Local-OTA for Embedded Linux System
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      • [X-Shield] Module of the Embedded Boards initialization
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由 GitBook 提供支持
在本页
  • Introduction
  • New feature
  • ARMv8 some basic concepts
  • Change log
  1. TECH
  2. ARM
  3. ARM-v8-A

02_ARMv8_基本概念

https://github.com/carloscn/blog/issues/1

Introduction

  • 新一代64位处理

  • 保持ARMv7兼容性

New feature

在programmer guide 2.1里面 引入那些feature:

  • Large physical address

    32位系统的没有enable的话,只支持4G。

  • 64bit virtual addressing

    使之虚拟地址空间可以超过4GB

  • automatic event sinaling

    支持原子操作的存储和访问的操作

  • larger register files

    减少对栈的使用,提高性能。

  • ...

  • Addtional 16KB 和64KB TLB

  • ...

  • Load-Acquire, Store Release instructions

  • NEON double-precision floating-points

ARMv8 some basic concepts

RM datasheet:

  • PE: Processing Element(处理机)

RISC架构的特性(RM提供的):

  • A large uniform register file. (ARMv7提供R0-R15,ARMv8提供更丰富的寄存器,比如X0-X30)

  • A load/store architecture, where data-processing operations only operate on register contents, not directly on memory contents.

  • Simple address modes, with all the load/store address determined from register contents and instruction fields only. (采用统一的简单的,比如内存映射MMU模式)

Execution States

The downward compatibility of ARMv7 shall be considered when the ARM designed the ARMv8 instruction set architecture,so the ARM designs the Execution State to be compatible with the ARMv7. There are the two types of `Execution State designed:

  • AArch64

  • AArch32

The two kinds of Execution State are like the different containers for different execution envs. In the lesson, the AArch64 execution state should be focused only. The difference between the AArch64 and the AArch32 exection states are showed as following table.

Features
AArch64
AArch32

General-purpose registers

31-64bits (X30 is used as the procedure link register)

13-32bits registers

Program Counter (PC)

one 64-bits registers

one 32-bits register

Stack Pointers (SP)

mulitple 64-bits registers

one 32-bits register

Exception Link Register (ELR)

mulitple 64-bits registers

one 32-bits LR register use as ELR

Procedure Link Register

one 64-bits, it is X30 register

Sharing the LR with the ELR as PLR.

Advanced SIMD vector/floating-point

32 128-bits registers

32 64-bits registers

Instruction Set

A64

A32 and T32

Excepiton model

4 excepiton levels, EL0-EL3 (ARMv8 Exception Model)

PE modes and maps this onto the Armv8 Exception model (ARMv7 exception Model)

Virtual Addressing

64 bits virual address

32 bits virtual address

Process State (PSTATE)

The A64 includes instructions that operate diectly on various PSTATE.

Constract with the AArch64, the A32 and T32 operate them directly and can also use the APSR, CPSR to access.

Instruction Sets

arm的指令集有以下几种:

  • A64

  • A32/T32

AArch64 (A64)

Uses 32-bit instruction encodings and fixed-length.

AArch32 (A32/T32)

A32 uses 32-bit instruction encodings samely, and fixed-length. However, the T32 is a variable-length instruction set that uses both 16-bit and 32-bit instruction encodings.

Note, in AArch32, the A32/T32 instruction sets were called ARM and Thumb instruction sets. The ARMv8 instrcution set extends each of these instruction sets.

种类

https://github.com/carloscn/doclib/blob/master/man/arm/armv8/arm64_quick_reference.pdf

System Registers

  • Format

  • Types [D13 chapter in RM]

Supported Data Types

  • Byte 8bits

  • Halfword 16 bits

  • Word 32 bits

  • Doubleword 64 bits

  • Quadword 128 bits

Exception Levels (RM-D1.1)

  • EL0

  • EL1

  • EL2

  • EL3

AArch64's Registers

  • R0-R30

  • SP

  • PC

  • V0-V31

R0-R30

31 general-purpose registers. Each register can be accessed as X0-X30 (all the 64-bit are used) in 64 bit mode, W0-W30 (only low 32-bit are used). The Wx are Xx low 32-bit.

SP

64-bit dedicated Stack Pointer register.

PC

A 64-bit Program Counter holding the address of the current instruction. Software cannot write directly to the PC. It can only be updated on a branch, exception entry or exception return.

Processor State (RM-D1.7)

Condition Flags

  • N

  • Z

  • C

  • V

Exception Masking bits

  • D

  • A

  • I

  • F

Exection Status Control bits

  • SS

  • IL

  • nRW

  • EL

  • SP

Change log

  • [2022年6月29日]: 更新arm寄存器分类的脑图

  • [2022年7月7日]:

    • 增加对arm指令集分类的介绍

    • 指令分类图

上一页ARM-v8-A下一页03_ARMv8_指令集介绍_加载指令集和存储指令集

最后更新于1年前

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